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Substrate noise problems continue to harass the design of a System-on-a-Chip (SoC). It is not obvious for the designer to identify the dominant substrate noise entry points. This paper proposes a new approach to gain insight in and predict the impact of substrate noise on mm-wave circuits. The approach is validated by measurements on a CMOS 48-53 GHz LC-VCO, designed in a UMC 0.13 mum technology.
Leading-edge CMOS provides transistor performance that, by traditional measures, is more than adequate for implementing millimetre-wave transceivers. Analogue and RF design is supported by device-level libraries and extraction tools. Simple extensions to these will allow rapid design cycles for millimetre-wave applications.
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