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Instruction set randomization (ISR) was proposed early in the last decade as a countermeasure against code injection attacks. However, it is considered to have lost its relevance; with the pervasiveness of code-reuse techniques in modern attacks, code injection no longer remains a foundational component in contemporary exploits. This paper revisits the relevance of ISR in the current security landscape...
To prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor...
ChaCha20 is an encryption cipher selected by Google to replace the now obsolete RC4 in the Chrome browser and Android devices. The current article discusses the performance implications of parallelizing ChaCha20 across multicore CPU and GPU. The serial implementation used to derive the parallel code is part of BoringSSL encryption library. We used OpenMP and OpenCL to accelerate the cipher and obtain...
Secure computation is increasingly required, most notably when using public clouds. Many secure CPU architectures have been proposed, mostly focusing on single-threaded applications running on a single node. However, security for parallel and distributed computation is also needed, requiring the sharing of secret data among mutually trusting threads running in different compute nodes in an untrusted...
Counter mode is one of the standard modes of operation for block ciphers. It has performance advantages due to its high parallelism. For a given key and a 96-bit IV, a 128-bit ciphertext block is computed by XOR-ing the corresponding plaintext block with the encryption of a unique 128-bit Counter Block. The Counter Block values are generated by incrementing a 32-bit counter that is concatenated to...
Key management using public key cryptography is less preferable due to several limitations like relatively high computation cost, encryption of preferably short messages, complex encryption-decryption algorithms etc. So we resort to private key management technique. In order to exchange messages between nodes in a Wireless Network, secret shared cryptographic keys must be established between the nodes...
We demonstrate that a certain class of side-channel attacks is feasible due to unintentional cache contentions between code segments in cryptographic applications. These inadvertent contentions should be considered as a flaw in the implementation of cryptographic applications, which necessitates a software analysis framework to identify their primary cause and check the effectiveness of proposed countermeasures...
We report our experiences in designing and implementing several hardware Trojans within the framework of the Malicious Processor Design Challenge competition. It was held as part of the Cyber Security Awareness Week (CSAW) at the Polytechnic Institute of New York University in November 2011. A malicious processor provides an attacker the ability to bypass traditional defensive techniques as they occupy...
The ICmetrics technology is concerned with identifying acceptable features in an electronic system's operation for encryption purposes. Ideally, the nature of the features should be identical for all of the systems considered, while the values of these features should allow for unique identification of each of the systems. This paper looks at the properties of the Program Counter of a processor core...
Enocoro is a family of stream ciphers proposed by Watanabe et al. in 2007. It consists of two algorithms called Enocoro-80 and Enocoro-128v1.1, whose key lengths are 80 bits and 128 bits respectively. In this paper, we show that Enocoro-128v1.1 is vulnerable against the related-key attack in which we assume a stronger attacker than one in the related-key differential attack. The attack is applicable...
To build secure SMP system with resistance against physical attacks, the essential requirements is to make data encryption and data authentication for both the shared bus and the shared memory. Analysis of such problem educes that it must combine the counter mode encryption with the hash tree based authentication, and such combination must inosculate with the architecture characters of SMP system...
In this paper, we provide a low cost AES core for ZigBee devices which accelerates the computation of AES algorithms. Also, by embedding the AES core, we present an efficient architecture of security accelerator satisfying the IEEE 802.15.4 specifications. In our experiments, we observed that the AES core and the security accelerator use fewer logic gates and consume lower power than other architectures...
Memory encryption offers a secure protection for the confidentiality of program and data. But implementing an encryption design for embedded processor is much difficult. As the embedded processor is highly constrained by the application requirement, the designers can't only concern with security. This paper proposes a new lightweight memory encryption cache (MEC) to obtain a balance among the performance,...
Hybrid hard drives (HHD) are coming up with potential high viability in mobile computing. It's quite necessary to put forward an efficient secure scheme for hybrid hard drives. NAND Flash of HHD is made full use as a container and a buffer for metadata. We propose an efficient combined scheme based on Galois/Counter Mode (GCM) to protect hard disk data by authenticated encryption, and build a secure...
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