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Security is the major aspect in any type of communication systems. The generation of secret keys randomly provides good security as well as better complexity in cryptographic based algorithms. In literature there exist symmetric key algorithms which use the same key for encryption as well as decryption. Among all the algorithms, Advanced Encryption Standard (AES) is used in many fields of security...
For the rapid response and security requirements of network communication, this paper develops a new implement method of encryption and authentication scheme SM4-GCM on FPGA with low resource occupancy and fast processing speed. This method adopts the SM4 algorithm with independent intellectual property rights. Two SM4 modules are used during encryption to improve the data processing speed by Ping-Pong...
This paper aims to present cube neutral bit tester on EPCBC. Cube neutral bit tester is a generic class of methods for building distinguishers, which find function approximating F(K, V) that depend on less than all key bits. We demonstrate how to use an efficient FPGA implementation cube neutral bit tester on the block cipher EPCBC. Different from the previous kinds of attack, the primary purpose...
An FPGA implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves high-speed with little hardware resources using feedback logic and inner pipeline with negative edge-triggered registers. In this way, the delay of the critical path is reduced, without increasing the latency of cipher execution. The proposed implementation reaches a data throughput...
Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses...
This paper introduces the principle of AES encryption algorithm and gives a detailed description of the algorithm FPGA design and implementation. The limitation of the current AES implementation methods is that the thruput is small. In allusion to this problem, this paper applies assembly-line technology in the designation and gains the best optimized area and speed. It implements AES encryption algorithm...
Recently, DES has been the most widely used symmetric block cipher for information security. But many powerful attacks, such as differential attack and linear attack had been proposed for cryptanalyzing DES. This paper gives an introduction and theoretical analysis of DES Algorithm and proposes a new design of encryption key and S-box to improve the algorithm performance. The hardware language VHDL...
In this paper, we propose a high-speed parallel GF(2128) bit multiplier for Ghash function in conjunction with its FPGA implementation. Through the use of Verilog the designs are evaluated by using Xilinx Vertax5 with 65 nm technic and 30,000 logic cells. The highest throughput of 30.764 Gpbs can be achieved on Virtex5 with the consumption of 8864 slices LUT. The proposed design of the multiplier...
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very...
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