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Current Network-on-Chip (NoC) architectures sometimes employ mesh or torus topology with the dimension-order routing. In this paper, we propose a deadlock-free routing algorithm, referred to as Balanced Dimension-Order Routing (BDOR), which provides the balanced minimal paths to each destination based on the simple routing regulations. Since the BDOR has the similar path regularity to that of the...
The rate of injecting packets into the network should be regulated carefully because the packet latency could increase rapidly if the network saturated. In order to solute this problem, we present a new flow control strategy which can be coupled with any routing algorithm. In particular, we introduce the notion of Injection Level, a set of values of injection rate. We expect to simplify the process...
Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different...
In this paper, we propose one hierarchical 2-D mesh network-on-chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount, communication data contention and bandwidth penalty to enhance the system overall performance of the new architecture. Modeling...
Building complex interconnect networks in a bottom-up way, for example by using self-assembling techniques, represents an ultimate challenge for building large-scale emerging computing devices. Due do the general lack of precise control over many self-assembling techniques, such interconnects are expected to be largely unstructured. In this paper we introduce two simple wire growth models for non-classical...
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