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This paper describes a macromodel of operational amplifiers for compressor circuit design. The macromodel allows to simulate the operational amplifier with single-power supply as well as double-power supply. The output waveforms using the macromodel are compared with those using the pre-set model only with double-power supply. The output voltages using the present macromodel are amplified in the region...
A new adaptive circuit design approach is proposed and analyzed employing independently biased back-gated Double-Gate MOSFET (DGMOSFET) devices. Threshold voltage tuning using back-gate of the DGMOSFET was compared with a conventional body-bias method. The technique is a promising solution to control the transistor's threshold voltage while reducing undesirable effects at the sub-50-nm device technology...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
A physical yet analytical phase change memory (PCM) model simultaneously accounting for thermal and electrical conductivities is presented. Due to the physics based nature of the model, the essential temperature from heating and cooling of PCM during operation is instantaneously updated. More importantly, the model can be applied to non-conventional circuit design technique. We show that for the first...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
The Philips compact MOS model, MOS MODEL 9, has been developed for the simulation of analogue circuits. With only 18 parameters mos MODEL 9 describes accurately the characteristics in the operating regions most important for analogue design [1,2]. Recently the capabilities of the model in describing various processes, with minimum channel lengths as low as 0.35 ??m, have been presented [1]. MOS MODEL...
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