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There is a continuously increasing demand for lower power consumption and higher operating frequencies in digital systems. In addition, external or operation-induced disturbances may significantly affect circuit functionality or performance. This paper analyzes the effect of power supply disturbances on the propagation delays of digital circuits implemented in Spartan-3A FPGAs and demonstrates that...
Accurate simulation of digital circuits is an essential part of the design process. High precision models are generally used to confirm logic behavior and estimate power dissipation, which has become an extremely important design parameter. Unfortunately high precision analysis is expensive in computer execution time, and there is always a trade-off between accuracy and speed. This work proposes a...
In this paper, we present a novel technique for online testing of feedback bridging faults in the interconnects of the cluster based FPGA. The detection circuit will be implemented using BISTER configuration. We have configured the Block Under Test (BUT) with a pseudo-delay independent asynchronous element. Since we have exploited the concept of asynchronous element known as Muller-C element in order...
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