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A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering supply voltage is possible. This SRAM cell is working under 0.3 V supply voltage offering a SNM improvement of 22% for the read cycle. Write Margin is not affected due to using body biasing technique. 65 nm ST models are...
This paper investigates the impact of random dopant fluctuation effect on surrounding gate MOSFET, from atomic statistical simulation of device to circuit performance evaluation. The doping profile is generated by an analysis of each lattice atom and then the threshold voltage variation is obtained by device drift-diffusion simulation. Then the circuit performance evaluation is performed by feeding...
Soft errors due to charged particle strikes at the sensitive cell nodes could modify the functionality of the design by changing the configuration bits of an SRAM based FPGA. However, with the development of very-deep-sub-micron (VDSM) or even the nano-technologies, aggressive device size has impacted severely the soft error rate of integrated circuits. In this paper, three new SRAM cell designs are...
Transistor sizing to control random mismatch is investigated. Input offset voltage of 65 nm bulk CMOS SRAM sense amplifiers are measured to analyze NMOS and PMOS threshold voltage (Vtn, Vtp) variation effects and compare them with statistical models and Pelgrom model predictions. A linear statistical response surface model (RSM) relating input offset to Vtn and Vtp is shown to agree well with measured...
Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation ULSI circuits. In this paper we propose a high performance voltage sense amplifier in sub 32-nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed design improves the sensing delay and shows excellent tolerance to threshold voltage mismatch...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
Data retention power gating is a commonly used method for leakage reduction in deep submicron SRAM. However, application of such methods result into reduced stability of the SRAM bitcell. Moreover, reducing supply voltage and increasing process variation put a limitation on such usage in deep submicron processes. Present scheme describes a method to enhance stability while applying such data retention...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
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