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A 10b 150MS/s 0.4mm2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gain-boosting, pseudo-differential output pair, and continuous-time...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
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