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We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work...
A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a...
It is widely-known that coupling exists between adjacent through-silicon vias (TSVs) in 3D ICs. Since this TSV-to-TSV coupling is not negligible, it is highly likely that TSV-to-TSV coupling affects crosstalk significantly. Although a few works have already analyzed coupling in 3D ICs, they used S-parameter-based methods under the assumption that all ports in their simulation structures are under...
4μm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified...
A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC)...
Three-dimensional (3D) stacking using through silicon vias (TSVs) is a promising solution to provide low-latency and high-bandwidth DRAM access from microprocessors. The large number of TSVs implemented in 3D DRAM circuits, however, are prone to open defects and coupling noises, leading to new test challenges. Through extensive simulation studies, this paper models the faulty behavior of TSV open...
Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC2 shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit...
3D chip-to-chip capacitive interconnections are in common practice characterized with FEM solvers as they cannot be modeled as lumped RLC circuits as ohmic 3D interconnects. This paper describes some drawbacks of this procedure and proposes an innovative flow, based on post-layout parasitic extraction tools, to enable the designer to place capacitive interconnects as constrained macros in a digital...
This paper discusses substrate coupling effects in 3D integrated circuits carried by TSV interconnects (Through Silicon Vias). These electrical couplings lead to several impacts on 3D circuit performance. RF (Radio Frequency) characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling and make obvious this phenomenon. New modeling...
This paper presents multilayered wideband filter (WBF) 10 GHz based on technology Low Temperature Co-Fired Ceramic (LTCC). WBF uses three-dimensionally (3D) coupled helical inductors. WBF exhibits 3-dB bandwidth 9, 3...10, 6 GHz (1, 3 GHz). The size of WBF is 2, 3??1, 6??0, 8 mm. The results of modelling were got in electrodynamics package CST MicroWave Studio 2009.
In this paper, we present a new 3D wirelength distribution model which considers the contribution of through-silicon-via (TSV) on wirelength, die area, and power consumption. Since TSVs occupy the device layer together with active devices, the die area increases if TSVs are utilized. This area overhead, which in turn affects the wirelength, worsens due to the large size of TSVs themselves, which is...
Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth, low-power, and low-latency chip-to-chip I/O. Chips are placed face-to-face, with only a few microns of separation, such that overlapping transceiver circuits can send and receive signals through capacitive or inductive coupling. Packaging chips in this way, however, presents a number of physical challenges...
This paper presents a solution of stacked chips using a capacitive communication from electrodes at the last metal layer with a wafer level assembly process. The wafer level approach instead of the die level allows high throughput and enables further optimization of the capacitive structures. To reach a good AC coupling an additional passivation layer was deposited then planarized and at the same...
This paper presents an algorithm that enables an extension of standard 3d capacitance extraction to take into account the effects of small dimensional variations of interconnects by calculating the corresponding capacitance sensitivities. By using an adjoint technique, capacitances and their sensitivities w.r.t. multiple geometric parameters can be obtained with one-time 3d extraction using the boundary...
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