The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
Network-on-Chip (NoC) with wireless interconnects is one of the potential solutions to overcome limitations of conventional NoC architectures over far-apart communications in multicore systems. Detailed investigations of Wireless NoC (WNoC) highlight their many benefits. But, idle-state power consumption associated with WI interfaces and routers is significantly high. To reduce the idle-state power...
This paper quantifies the difference in resource demand between modern and classic NoC workloads. In the paper, we show that modern workloads are able to better utilize higher numbers of VCs and smaller C factors in order to attain performance and energy efficiency. This is because of the high throughput and possible local congestions in their traffic pattern. As a result, such workloads are more...
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows...
In the recent trends the need for low power and less on-chip area is on high note for the portable devices. To cope up with the arising need, a new Magnitude Comparator is proposed with low power and less on-chip area for different range of lower supply voltages using Modified GDI technique implemented in 45nm process technology using CADENCE VIRTUSO. There is 95% and 67% reduction in power at lower...
Networks-on-Chip (NoCs) have been well accepted for energy efficient on-chip communications for multicore systems. But, a NoC router consumes considerable leakage power even when not in use. For large scale systems, number of unused routers at any time is reasonably high. A significant amount of this leakage power can be saved by applying fine-grained power-gating to unused routers in a NoC. In this...
Rapid growth in the cache sizes of Chip Multiprocessors (CMPs) to support high performance applications will lead to increase in wire-delays and unexpected access latencies. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (S-NUCA) has a fixed address mapping policy whereas dynamic NUCA (D-NUCA) allows blocks to relocate nearer to the processing...
In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended...
In this paper, one of AMBA (Advanced Microcontroller Bus Architecture) known as AMBA APB (Advanced Peripheral Bus) is designed which provides minimum power consumption and low bandwidth. For this, an APB Bridge with Reset Controller design has been implemented in Verilog language. Reset controller introduces a reset signal BnRES during Power-on Reset (POReset) conditions so that propagation of metastable...
For a standalone Fall Detection system based on computer vision we want to obtain a low power architecture to meet the real time processing, power consumption, energy constraints which also satisfy the high performance in recognition, and accuracy. In this paper, we present the different architecture explorations for Fall Detection system implemented on heterogeneous platform as Zynq-7000 AP SoC platform...
Power efficiency has been recognized as an important factor of the computing technology. On-chip caches represent a sizable faction of the total power consumption of microprocessors. Non-uniform cache access (NUCA) cache split the cache into several tiles, which enables the ability to power down some tiles at run time. We observed that some workloads have related small working set, thus we can dynamic...
Due to high latency and high power consumption in long hops between operational cores of NoCs, the performance of such architectures has been limited. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless Network-on-Chip (WNoC) has been emerged. Employing wireless communication links between cores, the new technology has reasonably increased...
Achieving lightning fast speed data communication in Chip Multi Processor (CMP) based systems as well as Networkon Chips (NoCs) is always desired for target performance. Data communication links inside the communication fabric of CMP or NoC architectures have strong impact on their performance and power dissipation. Several approaches exist to reduce power dissipation of parallel link on-chip interconnects,...
Power consumption in programmable devices has become a primary factor in design flow. Among the main concerns of power consumption, application performance, battery life, thermal challenges, or reliability, power consumption is crucial in FPGA designs for powered battery equipment. In this paper, we study the FPGA-based design for Sobel Edge Detection algorithm for low cost fall detector and we present...
Nowadays reconfigurable Network-on-Chip (NoC) is common high performance on-chip communication architecture for multi-core System-on-Chips (SoCs). This paper improved overall performance of reconfigurable NoC and throughput by using some extra switches and multiplexers. In the proposed architecture, some routers are replaced with 5-port switches. Simple 5-port switches are used for making a shorter...
As we move to integration levels of 1,000-core processor chips, it is clear that energy and power consumption are the most formidable obstacles. To construct such a chip, we need to rethink the whole compute stack from the ground up for energy efficiency — and attain Extreme-Scale Computing. First of all, we want to operate at low voltage, since this is the point of maximum energy efficiency. Unfortunately,...
In this paper, the proposed approach is assessed from not only its power-performance efficiency but also the accuracy of implemented algorithms on the real hardware environment. The real system treats pattern recognition and motion tracking. The former uses the subspace method and the latter adapts the Kanade-Lucas-Tomasi (KLT) algorithm. These algorithms are widely known in computer vision but the...
The De Bruijn topology, due to its interesting features such as a small minimal path, a small average latency and a small average number of hops, is a promising alternative topology to mesh-based NoCs for low-power applications. However, these advantages strongly depend on the efficiency of the routing algorithm in presence of congestion. This paper investigates efficient implementations of routing...
In this paper, a low-power delay-recycled all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC corrects the duty-cycle of the distorted clock to 50% under process, voltage, and temperature (PVT) variations. Besides, the delay-recycled architecture reduces the required length of the delay line to 1/2 of the input clock period. The proposed ADDCC architecture saves both the chip...
Network-on-Chip (NoC) architectures were proposed to solve scalability issues experienced in bus-based SoCs. They incorporate a communication infrastructure defined by topology, routers and switches, in order to provide a scalable and high performance network for the SoC resources while satisfying the constraints of embedded platforms. The choice of appropriate NoC topology depends on the desired...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.