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In an inevitable changing world where our ecology is deteriorating and renewable resource is at its critical stage left us with only one option: “Go Green”. It postulates to design energy-efficient and economic internet equipment, albeit a trade-off between performances versus power saving. But it is the demand of time to adore power saving rather performance for the sustainable and green earth. As...
With emerging high performance digital circuits, the need for data converters with high accuracy, high speed and low power for various kinds of applications has increased greatly. Extensive researches are being conducted in order to decrease the size of data converters to obtain low power and high speed characteristics. Digital to Analog Converters (DACs) convert digital signals to analog signals...
A novel pixel architecture for CMOS image sensors is presented. It uses only one amplifier for both integration of the photocurrent and in-pixel noise cancelation, thus minimizing power consumption. The circuit is specifically designed to be used in readout systems for lateral flow immunoassays. In addition a switching technique is introduced enabling the use of column correlated double sampling technique...
The unceasing shrinking process of CMOS technology is leading to its physical limits, impacting several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of promising technologies. Several works have been proposed so far, describing how to synthesize boolean logic functions...
Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present...
Networks-on-Chip (NoCs) have garnered significant interest as communication backbone for multicore processors used across a wide range of fields that demand higher computation capability. Wireless NoCs (WNoCs) by augmenting single hop, long range wireless links with wired interconnects; offer the most promising solution to reduce multi-hop long distance communication bottlenecks and opens up innumerable...
Power consumption in test becomes a higher barrier for consideration in test of any combinational circuit is high during test mode as in its normal mode of functioning as enormous power dissipation seriously affects the chip reliability. Many techniques are proposed to lower down the test power. In scan based design, rippling transition created by test patterns shifting along the scan chain not only...
In the context of coarse-grained reconfigurable systems we present a power estimation model to guide the designer in deciding which part of the design may benefit from the application of a power gating technique. The model is assessed by adopting a reconfigurable core for image processing targeting an ASIC 90 nm technology.
In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
The centralized Radio Access Networks (RAN) architecture is one of the promising approaches to reduce energy consumption of Base Stations (BSs), while BS sleeping technology can achieve further energy savings. In this paper, a power consumption model of the centralized RAN architecture is proposed, which has not been addressed before. Moreover, we analyze the existing BS sleeping schemes and compare...
The cloud radio access network (C-RAN) has become a promising architecture for future wireless communication system. In general C-RAN architecture, baseband units processing resource are centralized to form the baseband resource pool, which connects to remote radio units (RRUs) with the switching unit. In accordance with the traffic variation, the necessary on-state baseband resources are allocated...
Existing Data Center Network (DCN) architectures are classified into two categories: switch-centric and server-centric architectures. In switch-centric DCNs, routing intelligence is placed on switches, each server usually uses only one port of the Network Interface Card (NIC) to connect to the network. In server-centric DCNs, switches are only used as cross-bars, and routing intelligence is placed...
Data interaction between power consumers and utilities is one of the distinctive features of smart grid. The smart meter plays a core role in data collection and transmission process, which is also considered as one of the most power consuming devices in the whole architecture of distribution power grid. With the large-scale distribution of smart meters in high-density residential communities and...
By 2020, next generation (5G) cellular networks are expected to support a 1000 fold traffic increase. To meet such traffic demands, Base Station (BS) densification through small cells are deployed. However, BSs are costly and consume over half of the cellular network energy. Meanwhile, Cloud Radio Access Networks (C-RAN) has been proposed as an energy efficient architecture that leverage cloud computing...
This paper presents a new row decoding architecture implemented in 90nm STM10 triple well CMOS technology for low supply voltage, high speed NOR type Flash memories. The overall design is complemented with a novel stress relaxed high/low or positive/negative level shifter for converting the digital signals operating at 1.2V to higher supply voltages for high voltage applications. The proposed level...
Network on chip (NoC), a communication subsystem provides efficient communication between IP cores like data transmission between IP cores through link interface. This technology implies the parameters consideration and one main consideration is power. The power dissipated by the links through a network on chip starts to compete with the power dissipated by the other elements. Proposed Power reduction...
This paper presents a novel methodology for low power implementation of one and multidimensional discrete wavelet transform. The basic computation performed by forward and inverse wavelet transform is the computation of inner products between vectors of data (either input data or wavelet coefficients of previous stages) and filter coefficients. The proposed methodology aims at reducing the switching...
One of the greatest challenges in HPC is total system power and energy consumption. Whereas HPC interconnects have traditionally been designed with a focus on bandwidth and latency, there is an increasing interest in minimising the interconnect's energy consumption. This paper complements ongoing efforts related to power reduction and energy proportionality, by investigating the potential benefits...
The energy consumption is becoming a particular concern in Ultra Dense Networks (UDN), where thousands of small base stations (BSs) and access points are deployed in a narrow area. An applicable solution to mitigate the increased energy consumption is switching on/off the BSs in accordance with the traffic demand in the network. In the literature, it is shown that the selection of the optimal set...
The cell sleeping scheme is an efficient method for power saving in the cellular networks. The LTE heterogeneous network (HetNet) with mixed macro cells and small cells is considered in this paper, and we propose an energy efficient user association scheme based on cell sleeping of small cell networks. Given that some of the base stations in the HetNet can be switched off (cell sleeping) along with...
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