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Compressors are commonly utilized in multipliers for reducing partial products in a parallel manner. In this paper 7–3, 7–4, 8–3, 8–4, 9–3, and 9–4 compressors designed with adder circuits or multiplexer circuits were implemented in Altera EP2C70F896 FPGA and their performance compared in terms of number of logic gates used, cell area and power delay product (PDP) for an optimum recommendation for...
As the data traffic demand increases continuously, LTE Heterogeneous Networks (HetNets) with macro-cells and small-cells seems to be the best solution to enhance the quality of user experience by increasing the coverage and capacity of cellular networks. One of the important challenges in such networks is the user association problem. Several approaches have been proposed for this purpose: based for...
The deployment of small cell base stations within the coverage area of a macrocell base station serves as an important means of increasing energy efficiency. Furthermore, such a deployment also constitutes a key technology for future communication network markets. There is a shortage of research, however, on how to efficiently solve the problem of coverage holes (that is, specific locations or areas...
Typical Global Positioning System (GPS) receivers, which are increasingly used in many areas, consume too much energy due to heavy processing in a long time. This makes them not useful and sometimes even impractical for applications with high mobility or operating in obstructed regions where the GPS signal is present in short time. To address the problem, we propose a new design for a fast GPS receiver...
The future 5G communication will bring about the surge of traffic. The traffic of cellular network has great non-uniformity and volatility in space and time, which brings opportunities and challenges to the planning and management of cellular network. The energy consumption on base station (BS) accounts for more than 50% of the total energy consumption of the cellular network. Due to the space-time...
This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design, simulation and testing of the chip is presented along with an exploration of the multi-Vdd design space. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the delay range by 2.4 times and consumes...
In this paper, a low power 4-bit 400 MS/s standard cell based flash Analog-to-Digital Converter (ADC) is presented. The proposed flash ADC uses comparators based on the logic gates. Relationship between the input voltage and comparator reference voltage defines the output of comparator to be '1' or '0'. The comparator is followed by the gain booster and encoder. Low power consumption is achieved by...
Cloud radio access network (CRAN) has been proposed as a potential energy saving architecture and a scalable solution to increase the capacity and performance of radio networks. The original CRAN decouples the digital unit (DU) from radio unit (RU) and centralizes the DUs. However, stringent delay and bandwidth constraints are incurred by fronthaul in CRAN, i.e. the network segment connecting RUs...
Centralized Radio Access Network (C-RAN) has been recently proposed to increase network capacity, reduce energy consumption, and improve scalability. However, C-RAN requires an extensive modification to the current infrastructure, which results in a considerable deployment cost. In this paper, we conduct a techno-economic study to evaluate the migration cost of C-RAN, and we propose a methodology...
In this paper we present a data-driven power control (DDPC) approach to improve total cell throughput and energy efficiency of ultra-dense femtocells. Although femtocells can increase the capacity and coverage in an indoor environment, ultra-dense femtocells may consume a lot of energy and generate severe interference. We investigate a data-driven clustering approach to reduce co-tier interference...
In this paper, a novel modified 4T Content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main source of power consumption. The Proposed Modified 4T CAM cell based MSML design which reduces delay by 74%–95% with increases total power consumption and area compared with...
In this paper, register file design using pulsed latches is presented. Having some advantages in performance, area and power, pulsed latches represent an attractive implementation of register files. In addition, a proposed multiport register file architecture is introduced using single physical read/write ports to virtualize additional ports for read and write. The initial results show huge savings...
In this paper, a novel low power 4T content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main sources of power consumption. The proposed 4T CAM cell based MSML design reduces the area by 25%, delay by 11%–30% and total power consumption by 62% compared with 6T CAM...
Small cells have been proposed to improve the signal quality of cell edge users and enhance the serving coverage. But a large number of small cells will cause severe interference and high energy consumption. Hence, green communication is an important issue. The main contribution of this paper is to provide an interference-aware small cell on/off mechanism in a downlink heterogeneous network system...
There is no doubt that the CMOS technology scaling affects significantly the performance of the one-transistor one capacitor dynamic-random access memories (1T-1C DRAMs). In this paper, the effect of CMOS technology scaling and the change of the fabrication techniques of the access transistor and the cell-storage capacitor on the performance of DRAMs are investigated and discussed qualitatively. The...
Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted...
The demand for increasingly challenging data rates in cellular networks has motivated the pursuit to exploit abundant bandwidth at the millimeter waves (mmWave) spectrum, which offers large bandwidths and near free-space path loss for line of sight links. However, this solution comes at the cost of limited communication range. Thus, mmWave basestations (BS) are expected to be densely deployed to maximize...
This paper presents for the first time a TFET/CMOS hybrid CAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications like the IoT (Internet of Things). Proposed design is low power, area efficient and re-configurable i.e. can either be used as CAM or normal SRAM or as a combination of both. The simulation extractions for power and speed are done including wiring and...
This paper presents the implementation of Rijndael S-Box using combinational logic for the SubByte transformation in the Advanced Encryption Standard algorithm for ASIC. The main focus of this project is on achieving reduction in area occupancy and power consumption for the S-box module. We have realized an optimized implementation of the S-box in the Verilog HDL, and have subsequently synthesized...
This paper presents a high-speed energy-efficient analog-to-digital converter (ADC) with two-channel time-interleaving on an asynchronous pipelined-flash architecture for each channel. With use of multiple sampling paths as well as asynchronous control by a low-power 6-phase clock generation, the proposed ADC eliminates power-hungry and bandwidth-limited residue amplifiers without sacrificing the...
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