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Hamming distance search CAM is a hardware capable of fuzzy search. In the CAM which uses a neuron MOS inverter, the through current flows during search operation and the power consumption increases. In this paper, we propose a new Hamming distance search CAM with clock signals. By using clock signals, the proposed circuit can reduce unnecessary through current flowing during the search operation....
Interest in machine learning with Deep Neural Network architectures has exponentially increased since the adoption of Convolution layers and GPUs for faster and larger network sizes. The efficiency of this combination has been proved for many different modalities (speech, video, images, etc.). The next natural progression is to develop dedicated hardware architectures that eventually allows for online...
The unceasing shrinking process of CMOS technology is leading to its physical limits, impacting several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of promising technologies. Several works have been proposed so far, describing how to synthesize boolean logic functions...
This paper presents a novel technique to reduce the power and latency in content-addressable memories (CAMs). The first technique is to discontinue the unnecessarily subsequent search-line precharge process based on pipelined matchline searching operation. Speed is improved significantly since search-line registers are comparing in parallel. Meanwhile, the power consumption is also significantly reduced...
As the speed metric of Massively Parallel Multi-Processors System-on-Chip (MP2SoC) systems has increased over time, another metric has become more important: power consumption. Finding a tradeoff between power consumption and performance early in the design flow of MP2SoC systems in order to satisfy time-to-market is the design challenge of Electronic Design Automation (EDA) tools. This paper presents...
In this paper, Master Slave Match Line (MSML) design is adopted in conventional Content addressable memory (CAM) cell. The main objective of this design is to achieve Low power and high speed. MSML consists of two Master Match Line (MML) and two Slave Match Line (SML). The Circuit was implemented using Microwind tool in 45nm technology. Performance metrics such as power is compared with existing CAM...
Variable cache ways extending cache ways of mapped set to adjacent sets is proposed in literature. For w-way set associative cache, 2w ways are enabled in this architecture during address mapping. This paper proposes architecture to reduce the power consumption in this variable cache way architecture. A sequential circuit to enable occupied ways based on address mapping is introduced in level one...
For a standalone Fall Detection system based on computer vision we want to obtain a low power architecture to meet the real time processing, power consumption, energy constraints which also satisfy the high performance in recognition, and accuracy. In this paper, we present the different architecture explorations for Fall Detection system implemented on heterogeneous platform as Zynq-7000 AP SoC platform...
In this paper, the proposed approach is assessed from not only its power-performance efficiency but also the accuracy of implemented algorithms on the real hardware environment. The real system treats pattern recognition and motion tracking. The former uses the subspace method and the latter adapts the Kanade-Lucas-Tomasi (KLT) algorithm. These algorithms are widely known in computer vision but the...
Power consumption is a major concern in today's processor design. As technology shrinks, leakage power dominates the overall power consumption of the processor although it is expected that dynamic power gains relevance in future semiconductor technology. This is particularly relevant for the cache hierarchy, which contains an important percentage of the microprocessor transistors. In this work we...
To meet the global challenge of reducing greenhouse gas emissions and the explosive demand of wireless data traffic, green architecture design is becoming a critical issue for mobile network operators. Heterogeneous deployments of different cell types have been used to fulfill the challenges mentioned above. In this respect, a critical concern for operators is how to deploy small cells in a green...
This paper presents design and modeling of a highly efficient node-level DC uninterruptible power supply (UPS) in rack-level DC power architecture. In the previous research, we proposed the architecture of the highly efficient rack-level DC system combined with node-level DC UPS. This paper deals with the design and modeling of proposed node-level DC UPS.
The importance of deploying energy efficient networks has vastly increased due to the rapidly growing nature of power consumption of ICT industry. This requires redesign of networks or modification to existing networks that could prove to be energy efficient. In this paper, two telephone networks namely traditional Public-Switched Telephone Network (PSTN) and Voice over Internet Protocol (VoIP), are...
In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach,...
The selection of the optimal architecture for a system is done through a process called Design Space Exploration (DSE). This paper presents a novel hybrid exploration process for multi objective modular computing architectures to provide even faster means of architecture selection. The introduced exploration approach radically reduces the number of architectural variants to be analyzed during the...
H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a technique for reducing the amount of computations performed by H.264 intra prediction algorithm. For each intra prediction equation, the proposed technique compares the pixels used in this prediction equation. If the pixels used in a prediction equation are equal, this prediction equation is simplified...
In energy efficient high end computing, a typical problem is to find an energy-performance efficient resource allocation for computing a given workload. An analytical solution to this problem includes two steps: first estimating the performances and energy costs for the workload running with various resource allocations, and second searching the allocation space to identify the optimal allocation...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
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