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Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word. They suffer from either adequate protection against multibit failures or...
A current trend in digital signal processing is to reduce power and energy consumption. The use of asynchronous designs is one of the possible ways to achieve these goals, but the nature of these circuits requires different modeling schemes. We present in this paper our own model for a novel DSP architecture comprising multiple asynchronous cores and ALUs per core. Our approach shows how to match...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
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