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A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
We propose a novel distributed cross-layer optimization approach for cognitive radio wireless networks. A cognitive radio is a wireless device that is capable of sensing the prevailing environmental conditions and automatically adapting its operating parameters in order to enhance the performance of both the system and potentially the whole network. Given the lack of a centralized intelligence to...
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