The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 17% while preserving the average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared...
High throughput chip-level integration of communicating heterogeneous elements (CLICHE) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of high throughput CLICHE?? switch is decreased by 18% as compared to CLICHE?? switch. The total metal resources required to...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.