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We propose a technique that reduces static power consumption in caches with negligible hardware overhead and no performance penalties. Our proposed architecture achieves this by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in the immediate future by exploiting in-flight cache access information. We simulated our architecture using the Simple scalar...
DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1, 2] has been proposed to reduce the activation/ precharge power. However, those prior work either incurs significant performance degradation or introduces large area overhead...
An architecture for a high-speed Reed-Solomon decoder developed for digital VCRs is described. A maximum data rate of 16 MB/s and an error correction capability of 4-error- or 8-erasure-correction are realized using four-stage pipelines: a syndrome generator, a polynomial coefficient generator, a polynomial evaluator, and an error corrector. The polynomial coefficients are generated by a superscalar...
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