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This paper presents a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers. The ADC is designed...
A 12-bits 40 MS/s pipeline analog-to-digital converter (ADC) in SMIC035um mixed-signal process is presented in this paper. The ADC adopts methods below to improve its performance, a novel bootstrapped switch is used to sample and hold circuit in order to improve the resolution of ADC, a residue amplifier with gain-boost to eliminate gain error. This ADC achieves a SFDR of 65 dB, a SNDR of 56 dB, a...
A 10-b low-voltage CMOS pipelined analog-to-digital converter is described. A low-voltage technique is proposed for pipelined ADC that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough...
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