The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a Non-Binary LDPC decoder with information throughput of 2.267Gbps and power consumption of 212.4mW, yielding an energy efficiency of 93.7pJ/b, implemented in a 40nm CMOS technology. The employed code is long and high-rate without degree-2 variable nodes, resulting in a low error floor. A dual decoding algorithm scheme alleviates the computational complexity of decoding, realized...
This paper focuses on resource allocation in heterogeneous Ultra Dense small-cell Networks (UDNs), in which massive overlaid small cells are under the coverage of a macro cell. In UDN, both co-tier and cross-tier interference need to be taken into account. When increasing the deployment density of Small-cell Base Stations (SBSs) and the unreasonable energy usage, it results in serious interference...
In this paper we present a data-driven power control (DDPC) approach to improve total cell throughput and energy efficiency of ultra-dense femtocells. Although femtocells can increase the capacity and coverage in an indoor environment, ultra-dense femtocells may consume a lot of energy and generate severe interference. We investigate a data-driven clustering approach to reduce co-tier interference...
Energy consumption's increasing importance in scientific computing has driven an interest in developing energy efficient high performance systems. Energy constraints of mobile computing has motivated the design and evolution of low-power computing systems capable of supporting a variety of compute-intensive user interfaces and applications. Others have observed the evolution of mobile devices to also...
In this paper, a high-flexibility and energy-efficient reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word (VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic...
The continuous demands on increased spectral efficiency, higher throughput, lower latency and lower energy in communication systems imposes large challenges on appropriate channel coding schemes and their efficient hardware implementation. Consequently, channel coding is not only a matter of information theory but also more and more knowledge on efficient parallel hardware architectures and underlying...
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency...
The rapidly increasing penetration of smart phones and the associated exponential growth in the wireless data traffic result in an increasing energy consumption and, consequently, greater carbon dioxide (CO2) emissions. However, on account of operational costs and environmental worries, this increase should be taken into consideration for future cellular networks evolution. In this paper, we study...
As the Information and Communication (ICT) infrastructure continues to evolve, throughput and energy efficiency have become key metrics. This talk explores FPGA-based parallel architectures and algorithms for a variety of streaming applications arising in Telecom and Big Data. We show high performance accelerators for deep packet inspection, regular expression matching, packet classification, traffic...
We propose a new approach for jointly scheduling deep sleep and allocating pilot and data transmit power in small cells with the aim of minimising energy consumption while maximising user utility within a mixed macro/small cell network. Our approach exploits the relatively predictable nature of traffic load across each day/week and is demonstrated to achieve an average energy reduction of 37%, and...
With the widespread development of cloud computing and high speed communications, end users store or retrieve video, music, photo and other contents over the cloud or the local network for video-on-demand, wireless display and other usages. The traditional I/O model in a mobile platform consumes time and resources due to excessive memory access and copying when transferring content from a source device,...
This paper presents an energy-efficient VLSI architecture for 8×8 2-D DCT, which relies on a fast and precise implementation of the LLM algorithm. The energy-efficiency is achieved by using a combinational 1-D DCT block that explores the algorithm's intrinsic parallelism and the integer constant multiplications. The target throughput of 19 Mpixels/s, which is required for VGA@30fps, is achieved by...
Global warming and climate changing is among the major challenges in the 21st century. In wireless communications, green architecture design is an urgent demand for operators, not only because of the social responsibilities but also their willingness to reduce the network construction and operating cost. Previous literatures tried to tackle deployment cost and energy efficiency in a separated manner...
Power consumption is becoming a concern in programmable logic design as the size and performance of modern FPGAs increase. Data-parallel applications can work on different parallelism level so as to achieve different performance. This paper presents an investigation into the best parallelism degree-operating frequency tradeoff in order to find the optimum number of instances for each parallelizable...
In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors. Several studies have suggested that it may be worthwhile to off-load execution of the operating system (OS) to one or more of these cores, or reconfigure hardware during OS execution. To be effective, these techniques must...
An automated architecture optimization for DSP algorithms within graphical Matlab/Simulink environment is proposed. The optimization uses Integer Linear Programming for scheduling and retiming of hardware blocks. The high-level block-diagram based Simulink model maps to FPGA or ASIC. Users can control the tuning range of architecture parameters and select solutions from energy-area-performance tradeoff...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.