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This paper presents an automatic gain control (AGC) circuit targeting 250 MHz IF applications based on a combined control loop: a fast settling feedforward loop performs coarse gain adjustment, while a conventional feedback loop realizes final fine gain tuning. The AGC consists of a low-voltage broadband CMOS programmable gain amplifier and the loops are implemented making use of novel peak detection...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
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