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This paper presents a new parallel processing wire routing machine, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip. A hardware implementation with concurrent time-multiplexed wavefront propagation from all terminals of a net is described. The new design requires fewer clock cycles to find the shortest path than the existing parallel routing algorithms. The time-multiplexed...
This paper presents a new parallel processing wire routing algorithm, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip or a PCB. A VHDL code is written to implement the algorithm on a prototype 4times4 and 8times8 single layer grid. Two methods are proposed for the design of processing element. The algorithm has been successfully tested on a XC2VP30 Virtex-II Pro...
It is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of (1) the rising sophistication of attacks requiring more complex analysis to detect, (2) the relentless growth in the volume of network traffic that we must analyze, and, critically, (3) the failure in recent years for uniprocessor performance to sustain the exponential gains...
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