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Image compression is one of the key image processing techniques in signal processing and communication systems. Compression of images leads to reduction of storage space and reduces transmission bandwidth and hence also the cost. Advances in VLSI technology are rapidly changing the technological needs of common man. One of the major technological domains that are directly related to mankind is image...
Advancements in digital electronics and signal processing algorithms for various purposes generated the possibility and need for designing artificial neural networks in hardware. The selected platform, FPGA, enables fulfillment of their demands and provides comfortable work and test environment. This paper presents development cycle and specifics for implementation of high speed Hamming artificial...
This work presents an optimized Implementation on Field Programmable Gate Array (FPGA) Architecture for an Infomax algorithm based on Independent Component Analysis (ICA). We use this algorithm to solving Blind Source Separation (BSS) problems in real-time mixed signal processing in order to clean speech signals under noisy environments and to probe the potential of this kind of algorithms embedded...
This paper presents FPGA-based ECG signal classification based-on a parallel genetic algorithm and block-based neural network. The proposed parallel genetic algorithm has cellular-like structure which is suitable for hardware implementation. With online learning using hardware parallel genetic algorithm to block-based neural network, the complete ECG signal classification can be implemented in hardware...
This paper discusses implementation issues of FPGA and ANN based PID controllers. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. This paper discusses the issues involved in implementation of a multi-input neuron with linear/nonlinear excitation functions...
A Neural Network (NN), implemented in 0.35 mum CMOS technology, was integrated in order to increase the distance range of a phase-shift laser range-finder and to achieve surface discrimination. The overall sensor was validated for well defined experimental conditions. Then, a digital updating system was developed, so that the embedded sensor achieves its task autonomously onboard the application,...
This paper shows the design possibility of a parameterizable implementation of neural multi-layer network on FPGA circuits (Field Programmable Gate Array) through the use of Handel-C language. The algorithm used for the training is the back- propagation. The tools of implementation and synthesis are the DK 4 of Celoxica and the ISE 6.3 of Xilinx. The targeted components are XCV2000 on Celoxica RC1000...
For the shortage of the traditional sink nodes of WSNs in refining and compressing the uplink data, a new method is proposed to design and implement a super sink node with the hardware fusion technology. This method adopts FPGA as the platform of the node and applies BP neural networks with systolic array structure, map arithmetic, stream line and nonlinear activation functions to achieve the hardware...
This paper presents an adaptive/evolvable hardware architecture and its FPGA implementation. The adaptive hardware is based-on evolvable block-based neural network (BBNN) and a cellular compact genetic algorithm (CCGA). The BBNN consists of a 2-D array of modular neuron. The CCGA has a cellular-like structure. A proposed layer-based architecture provides a solution for integration between BBNN and...
This paper explores the significant practical difficulties inherent in mapping large artificial neural structures onto digital hardware. Specifically, a class of weightless neural architecture called the enhanced probabilistic convergent network is examined due to the inherent simplicity of the control algorithms associated with the architecture. The advantages for such an approach follow from the...
We present a technique and algorithms to solve the following problem: Given both a Neural Network trained to classify a set of images, along with a set of floating-point hardware blocks (in reconfigurable logic), find the arrangement of blocks that achieves the best mix of precision, resources and speed with respect to a given cost function. We first illustrate the technique in detail by using a small...
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