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Adiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock...
This paper presents a high-voltage output stage producing signals well beyond the voltage ratings of standard devices in a nanometer-scale CMOS technology. The driver is a two-level, switched capacitor output stage that combines both voltage conversion and pulse drive. The design is highly modular and enables extended device-stacking seamlessly and with little overhead. The driver achieves a peak...
In this work we propose a technique for bootstrapping CMOS switches in voltage doublers and double charge pumps. The technique prevents short-circuit losses, improves driving capability, and enables efficient operation at low supply voltages. The effectiveness of our approach is verified through simulations of design examples, which also illustrate the improvements in conversion efficiency, voltage...
Power analysis attacks are a common and effective method of defeating cryptographic systems. Many power-analysis-resistant digital circuit techniques have been previously proposed, leaving the circuit designer a myriad of choices without a simple way to compare and contrast the strengths and weaknesses of each technique. In this paper, we compare four promising power-analysis-resistant digital logic...
Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both...
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