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Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest because of its characteristics of nonvolatility (i.e., zero standby power) and small cell size (i.e., high density and high performance). As the technology node is scaled down, however, the sensing margin of the STT-RAM is degraded because of the increased process variation and reduced supply voltage. To improve...
The threshold voltage (VT) drift induced by negative bias temperature instability (NBTI) weakens PFETs, while positive bias temperature instability (PBTI) weakens NFETs fabricated with high-k metal-gate, respectively. These long-term VT drifts degrade SRAM cell stability, margin and performance, and may lead to functional failure over the life of usage. Additionally, most state-of-the-art SRAMs are...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
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