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The de-synchronization methodology, which directly converts a synchronous circuit into an asynchronous counterpart according to the physical structure of pipelines, is very popular for its simplicity. However, the simplicity of the design methodology also introduces some power redundancy and performance reduction to de-synchronized circuits. This paper firstly investigates the influence of actual...
A high-speed dual-phase domino circuit design with high performance and reliable characteristics is proposed. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology. The test chip shows a...
This paper presents the methodology of converting an asynchronous design to a synchronous design. As the size of transistor is shrinking, the difficulty of a design to meet the timing has increased. Continuously shrinking of transistor size from time to time has increased the on-die variation such as Process, Voltage, and Temperature (PVT) variation of the chip. Since Performance Verification (PV)...
Asynchronous logic design has gained more and more interest over the last few years. However, as many designers are well aware, there exist various different and mostly diverse asynchronous design methodologies. In order to obtain a highly optimized circuit implementation, it is often necessary to mix different techniques for exploiting their specific benefits. Consequently, the need for efficient...
The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism...
Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (τ) has been expected to scale proportionally to the gate delay 'FO4'. Recent measurements, however, have yielded counter-examples showing a degradation of τ with scaling. In this paper we present these...
This paper reviews real-time (RT) Ethernet and discusses special requirements for numerical control (NC). Then such a real-time Ethernet - EtherMAC (Ethernet for Manufacture Automation Control) is presented. EtherMAC uses master-slave communication structure. The master device supports standard Network Interface Card (NIC), and the slave device has a modified one - removing CSMA/CD (Carrier Sense...
Asynchronous circuits have a number of potential performance advantages over their synchronous equivalents due to the ability to exploit average case performance. These advantages are offset by the loss of performance caused by the handshaking overheads which causes designs to be throughput bound. This paper investigates the nature of the throughput problem and proposes a novel automatic approach...
In this paper, a VHDL model of a second-order all-digital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability...
The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle...
High runtime failure rate as a result of reliability detractors is one of the major challenges for scaled-CMOS as well as emerging nanotechnologies. This results in multiple faults during life time operation. In this paper we propose a self-timed asynchronous architecture which can tolerate multiple transient bit-flips. This architecture has self-timed property, making it robust against delay variations...
Synchronous elastic circuits help synchronous designs tolerate computation or communication latencies, in a way similar to the asynchronous design style. The datapath is made elastic by turning registers into elastic buffers and adding a control layer that uses handshake signals and join/fork controllers. Join elements are the objective of two improvements discussed in this paper. The first one is...
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumption. In this direction, this paper focuses on a GALS system where the NoC and its end-nodes have independent clocks (unrelated in frequency and phase) and are synchronized via dual-clock FIFOs at network interfaces. Within...
Flip flops used to store a bit in a register have different requirements to flip flops used in a synchronizer application. The D input must be held stable during the setup and until the Q output appears, these times determine the remaining part of the clock cycle available for computing. On the other hand the D input can violate setup and hold times in a synchronizer, and the reliability of the synchronizer...
The GSI Event-Driven TDC GET4 is the first prototype of a high resolution low power event-driven TDC for the CBM-time of flight detector readout. The design specifications according to the CBM-ToF requirements are a very high time resolution of better than 25 ps and a double hit resolution of less than 5 ns. The TDC has to cope with an event rate up to 100 kHz per channel. The time core architecture...
This paper makes research on automatic gating clock technology in SoC clock network. Based on SoC1000 CPU core, analyze the characters of its inner time logic and combine ASIC physical design flow and method based on standard unit. This paper puts forward a clock network scheme based on precise credible time analysis. This method can greatly reduce SoC clock dissipation and at the same time, it can...
With the advent of networks-on-chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC...
Synchronizer characterization is non-trivial. The exponential response to parameter changes makes this task a challenge, which is further hampered by numerical instability and precision limitations of circuit simulators. The analysis of multi-stage synchronizers is extremely difficult due to the compounding of these exponential factors. We present results and discoveries from analyzing a variety of...
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rather than from behavioral description, which can be synthesized to RTL via high-level synthesis (HLS). Sequencing overhead is one of the factors for this performance gap; the choice between latch and flip-flop is not typically...
In this paper, a novel scheme is proposed for the implementation of FPGA based digital systems using asynchronous pipelining technique. To control the asynchronous data flow between stages, an intelligent controller is designed which decides the delay of each stage depending upon the magnitude of the input data (Data Dependent Delay). The intelligent controller has been designed using NIOS II soft...
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