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In this paper we present a fault tolerant Mesh based Network-on-Chip design that helps to tolerate router faults along with core recovery mechanism. Spare links are used to provide a connection to horizontal and vertical routers pivoting the failed one. To compliment the modified topology a routing algorithm has been developed that uses minimal and non minimal paths to communicate between source and...
Effective fault tolerant techniques are crucial for a Network-on-Chip (NoC) to achieve reliable communication. In this paper, a novel VLSI architecture employing redundant routers is proposed to enhance the fault tolerance of an NoC. The NoC mesh is divided into blocks of 2×2 routers with a spare router placed in the center. The proposed fault-tolerant architecture, referred to as a quad-spare mesh,...
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