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Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate. Check node processing is one bottleneck in NB-LDPC decoding. Various techniques have been proposed to simplify the check node processing. Particularly, the computation complexity can be reduced by employing an iterative forward-backward...
Non-binary low-density parity-check (NB-LDPC) codes can achieve higher coding gain than binary LDPC codes when the code length is moderate at the cost of higher complexity. One major step of NB-LDPC decoding is check node processing. Previously, iterative forward-backward approaches are employed to implement this step. However, the storage of the intermediate results of the forward and backward computations...
In this paper, we propose an improvement of the previously proposed decoder for split LDPC codes defined over finite groups. The output of the check nodes is adjusted such that it bears better resemblance to that of more complex and efficient algorithms. There is a significant improvement in the decoding performance with almost no oeffect on the decoding complexity. The hardware architecture for the...
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding architecture are developed to implement the...
Low density parity check (LDPC) codes over GF(2m) show significantly higher performances than binary LDPC codes. However, the hardware complexity and area of the decoder are largely increasing. In this paper, putting the code and decoder design together to consider, we propose a FPGA semi-parallel implementation of extended min-sum (EMS) decoding algorithm for quasi-cyclic low density parity check...
In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC (NB- LDPC) codes, presented in [4]. To the knowledge of the authors this is the first implementation of an GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the NB-LDPC decoders, together with a significant...
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