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The applicability of the Viterbi add-compare-select (ACS) functional block to both convolutional and LDPC codes in various parallel implementations is investigated. To this end, a trellis representation for arbitrary LDPC codes must first be established. Then, a high-level architecture for a Viterbi-algorithm-based unified decoder is proposed. An in-depth exploration of the crucial path metrics (i...
In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. This paper presents a multi-core architecture which supports convolutional codes, binary/duo-binary turbo codes, and LDPC codes. The proposed architecture is based on Application Specific Instruction-set Processors (ASIP)...
In this paper, we undertake a comparison of LDPC (768,384) and convolutional (171,133) codes for 60-GHz OFDM-based wireless communication systems. The comparison is based on two parameters: Frame Error Rate (FER) for 60-GHz channels and decoding hardware complexity for a required throughput of more than 1 Gbps. Additionally, we provide performance parameters of a fully parallel LDPC decoder chip,...
In this paper we present a multi-mode decoder architecture for convolutional codes and structured low-density parity-check (LDPC) codes based on a novel computation unit that is able to process Min-Sum as well as Add-Compare-Select (ACS) operations. Realized as application-specific instruction set processor (ASIP), this allows decoding of a vast number of different channel codes and implementation...
In this paper, we present a novel high-speed dual-core programmable decoder architecture for LDPC convolutional codes and their tail-biting versions. This architecture uses a modified Min-Sum algorithm and enables the decoding of a multitude of codes with different node degree distributions, rates and block lengths. We show how the parallelization concepts are derived using the properties of the bipartite...
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