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In this paper, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. Since SPM can reduce the access frequency to the cache, we find it is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without...
Realistic formal specifications of machine languages for commercial processors consist of thousands of lines of definitions. Current methods support trustworthy proofs of the correctness of programs for one such specification. However, these methods provide little or no support for reusing proofs of the same algorithm implemented in different machine languages. We describe an approach, based on proof-producing...
This paper presents an efficient technique for addressing in radix-2 FFT architectures. The novel addressing organization provides parallel load and store of the data involved in a radix-2 butterfly computation. The addressing scheme is based on a permutation of the FFT data, which leads to the minimization of the address generating circuit and the butterfly processor control. The paper proves the...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
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