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Branch Prediction Units (BPUs) are widely used to reduce the performance penalties caused by branch instructions in pipelined processors. BPUs may be implemented in different forms: the Branch History Table (BHT) is an effective solution when the goal is predicting the result of conditional branches. In this paper we propose a method to generate test programs able to detect faults affecting the memory...
Multiple-block prediction has been an exciting research area in the vast expanse of computer architecture. Block based trace cache was a valid proposal to feed the execution units with enough instructions so that the utilization of the execution units is to the fullest in a superscalar architecture. The block based trace cache aligns and stores instructions at the basic block level instead of at the...
Branch Prediction Units (BPUs) are highly efficient modules that can significantly decrease the negative impact of branches in superscalar and RISC processors. Traditional test solutions, mainly based on scan test, are often inadequate to tackle the complexity of these architectures, especially when dealing with delay faults that require at-speed stimuli application. Moreover, scan test does not represent...
Meeting the future requirements of higher bandwidth while providing ever more complex functions, future network processors will require a number of methods of improving processing performance. One such method will involve deeper processor pipelines to obtain higher operating frequencies. Mitigation of the penalty costs associated with deeper pipelines have achieved by implementing prediction schemes,...
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