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The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores with a lightweight point-to-point interconnect. However, such interconnects make snooping impractical and, thus, require...
Software related issues such as code/data mapping, highlevel communication management and power control are becoming increasingly important as we move towards NoC(network-on-chip) based CMPs (chip multiprocessors). This paper presents an ILP (integer linear programming) based formulation of the problem of communication energy minimization in such architectures. This formulation can be used for selecting...
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