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Transmission lines are becoming of common use at mm-wave to implement on-chip functions as impedance matching, filtering and interconnects. Lack of an accurate and fast simulation method is nonetheless evident for transmission lines in scaled CMOS where metal dummies inserted for IC planarization make their physical structure extremely complicate. Although lines are not uniform due to displacement...
Coplanar waveguide transmission lines and vertical interconnects are implemented on a thick (15 mum) Parylene-N dielectric layer over a lossy CMOS-grade Si substrate. Devices are measured up to 40 GHz and show very low loss behavior. Low loss tangent and low dielectric constant characteristics of Parylene-N result in significant improvement of transmission lines and interconnects compared to those...
We present design aspects and techniques for millimeter-wave circuits implemented in 65-nm CMOS. Different transmission line topologies are discussed and measurement results for a conventional coplanar waveguide and slow-wave coplanar waveguide implemented in 65-nm CMOS are shown. The attenuation of the on-chip transmission lines can be reduced by using slow-wave coplanar waveguides. A 1-stage cascode...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
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