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With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
This paper formulates and studies a model of neural network under a time-varying environment. Without assuming the smoothness, monotonicity and boundedness of the activation functions, the existence and global exponential stability of an unique equilibrium are investigated. Ourap-proach is based on the Brouwer's fixed point theorem, Banach fixed point theorem, and Halanay-type inequality.
We introduce a property of boolean functions, called transitivity which holds of integer, polynomial, and matrix products as well as of many interesting related computational problems. We show that the area of any circuit computing a transitive function grows quadratically with the circuit's maximum data-rate, expressed in bit/second. This result provides a precise analytic expression of an area-time...
This paper describes a new approach to the design of combinational logic using large-scale-integrated (LSI) circuit technology. A simple "prototype" logic function of n binary variables is imbedded within an array of at most (n+1) rows and columns. The cells of this array contain 2-input exclusive-OR gates, and its rows are fed by the input variables and logical "1". Its column...
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