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In this paper, we propose models for single and coupled on-chip global interconnect lines by distributed RLGC parameters using state space approach. Models for single and coupled lines are validated by comparing with SPICE simulations. Interconnect performance metrics are obtained from the proposed models for 65 nm, 90 nm, 130 nm and 180 nm technology nodes based on PTM values. In case of coupled...
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel...
With the continuing increase of chip density and the shrinkage of feature size of transistor in VLSI circuits, high temperature has become a concerned issue. High temperature not only decreases the functionality and reliability of chips, but also causes high package cost in order to cool down the system. For design consideration, one important issue related to temperature is how hot the chip may be...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
In this paper, we study bandwidth management of a wireless/optical based access/metro network in support of voice and data services. For voice services, we use a finite state Markov Chain to estimate the blocking probability of voice circuits over an Adaptive modulation and coding wireless channel, as a function of the channel parameters. For data services, we evaluate a rate matching and a buffer...
In this paper, we focus on the security issue of a chaotic digital communication scheme called chaotic-pulse- position modulation. We design a third party intrusion scheme to test to see if CPPM is as secure as is claimed. Experiments are conducted with various chaotic maps, where CPPM is used to modulate the message at the transmitter and a Kalman filter fed with a polynomial approximation is used...
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