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Computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according...
E-commerce (EC) over open devices and networks poses security challenges of a new dimension. This article presents a multi-party contract signing (MPCS) protocol to demonstrate how to apply the secure EC protocols to trading terminals supported by trusted computing (TC) technology. The protocol here reduces the number of rounds to two and the message transmission number to O(n2), which is the best...
A hierarchy transaction-level architecture consisting of physical layer, transport layer, transaction layer and application layer can improve system-on-a-chip (SOC) verification reliability and efficiency greatly. Transport layer of the hierarchy transaction-level architecture is responsible for end-to-end message transmission between software side and hardware side without caring about modules of...
In order to convert High Level Language (HLL) into hardware, a Control Dataflow Graph (CDFG) is a fundamental element to be used. Otherwise, Dataflow Architecture, can be obtained directly from the CDFG. In the 1970s and late 1980s, the Dataflow Model was the focus of attention that provided parallelism in a natural form. In particular, dynamic dataflow architecture can be generated to produce a high...
Multi-core architectures have spurred the rapid growth in high-end computing systems. While the vast majority of such multi-core processors contain symmetric hardware components, their interaction with systems software, in particular the communication stack, results in a remarkable amount of asymmetry in the effective capability of the different cores. In this paper, we analyze such interactions and...
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