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As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique for reducing MUXs, especially during the earlier design phase, has been demanded. This paper presents a novel MUX reduction technique in high-level...
Reducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the objective of minimizing power consumption of storage using dual-Vdd. Specifically, we propose a complete design framework that starts from dual-Vdd scheduling,...
IEEE P1900.4 is an emerging standard for optimized radio resource utilization where cognitive radio technologies are used for efficient spectrum utilization. In this paper, we design and implement a cognitive wireless network system based on open documents of IEEE P1900.4, and evaluate its performance using UDP streaming and HTTP download. Our experiments show interesting results that total network...
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