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Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20μm induced the maximum compressive stress of ~1 GPa at the...
3D (three-dimensional) wafer stacking technology has been developed extensively recently. Among many technical challenges in 3D stacked wafers the wafer warpage is one of the important processing issues to be resolved because the wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, WIW (within wafer) non-uniformity and...
Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated...
To meet future 3D stacking requirements on wafer-to-wafer level, we successfully demonstrate oxide-oxide direct bonding on 200 mm with and without copper level utilizing face-to-face alignment and bonding within one process module as well as on the same chuck.
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