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Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Cu TSVs with the diameter of 20μm induced the maximum compressive stress of ~1 GPa at the...
Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated...
This paper presents symmetrical counter-bonding as a method for integrating multiple substrates of noncompatible thermo-mechanical properties. This technique is successfully applied to fabricate MEMS tuneable high-impedance surfaces combining four substrates of two otherwise fabrication-incompatible materials (silicon and AF45 glass) on a wafer-level. A large-scale high-impedance surface with 200...
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