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Thinning down large scale integrated-chip (LSI) wafers to below 50 µm thickness is inevitable for the wafer-to-wafer (WtW) process as well as chip-to-wafer (CtW) or chip-to-chip (CtC) processes in three-dimensional LSI integration. In this work we have optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for WtW integration of 12-inch LSI wafer with thickness...
Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness ~10 μm) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient...
Micro-Raman spectroscopic technique has been employed to study the induced stress/strain by the metal microbumps in 3D-LSI Si die/wafer after wafer thinning and bonding, and the impact of bump spacing, bump size, bonding temperature and bonding force in the stress distribution in such a microbump bonded LSIs has been investigated. It is inferred that (i) the Si present at the interface (between CuSn...
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