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Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
Design and characterization of a new generation of single-photon avalanche diodes (SPAD) array, manufactured by ST-Microelectronics in Catania, Italy, are presented. Device performances, investigated in several experimental conditions and here reported, demonstrate their suitability in many applications. SPADs are thin p-n junctions operating above the breakdown condition in Geiger mode at low voltage...
Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. In order to utilize these test chips to measure stresses over a wide range of temperatures, one must have values of six piezoresistive coefficients for n- and p-type silicon over the temperature range of interest. However, the literature provides limited data...
Sink mobility has become an increasingly important requirement of various sensor network applications. Handling such mobile sink conditions brings new challenges to large-scale sensor networking. This investigation proposed a hybrid-structure routing protocol (HSRP) that combines the benefits of grid-based and cluster-based structures. Grid-based structure is designed to solve the cluster head selection...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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