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A partial parallel architecture for LDPC (Low Density Parity Check Code) decoder is proposed. The overall architecture is based on MIMD (Multiple Instruction Stream Multiple Data Stream), the internal calculation unit is based on SIMD (single instruction Stream multiple data Stream). The processor uses the programmable method to realize the NMS (normalized minimum sum) decoding algorithm, can get...
With advancement and scaling in Integrated circuit design, the accuracy of clock circuitry plays an increasingly important role. Timing precision is important to reduce the synchronization problem in digital circuits. The precise timing of pulse is also extremely important for designing asynchronous circuits. Delay element is the basic building block for asynchronous circuits. Many circuits of digitally...
In order to reduce the system computation complexity and delay, we propose a scheme to decrease the iterative time of the carrier synchronization for low-density parity-check (LDPC) codes. The system will stop iteration if the log-likelihood ratio (LLR) message at the output of decoder satisfies the limitary conditions. Simulation results show that the proposed scheme is efficient and there is little...
We consider serially-concatenated coding schemes over channels impaired by insertion, deletion, and substitution errors. Specifically, we focus on the interleaved concatenation of an outer channel code with error-correction capabilities and an inner marker code with synchronization capabilities. To limit the decoding latency, marker code-based synchronization is performed only once per received packet,...
In this paper, we propose the design method and the structure of a decoder with shortened cyclic code for radio data systems (RDS). Without microprocessor the logic gates are used to implement the hardware of the decoder, moreover, the decoder not only can decode the received message of RDS, but also has the functions of synchronization, error detection and error correction. The proposed decoder includes...
In this paper we propose an adaptive data hiding method that divides the host image in suitable and ineligible blocks. This classification is based on the DCT energy features from the horizontal, vertical and diagonal frequency information. Only the suitable blocks are used for data embedding using quantization index modulation (QIM). After the composite image is attacked by JPEG compression, a desynchronization...
We present in this paper a blind frame synchronization method based on the adaptation of the parity check matrix of the code. The blind synchronizer is initially based on the calculation of the log-likelihood ratios (LLR) of the syndrome elements, obtained using the parity check matrix of the code. Before applying our synchronization procedure, we propose in this paper to rearrange the parity check...
The communication manager module embedded in a dedicated system configurable via Internet design description and XILINX Spartan 3 FPGA implementation are presented. Keeping Internet connectivity as a priority, minimum subsets of IEEE 802.3 standard rules for Ethernet data interchange and RFC826 and RFC791 recommendations for address resolution protocol (ARP) and Internet protocol (IP) respectively,...
We investigated the accuracy of estimated synchronization positions for audio digital watermarking using the modified patchwork algorithm (MPA) on analog channels. We focused our efforts on synchronization since correct synchronization of DCT frames is crucial for watermark detection using this algorithm. We employed M-sequence synchronization patterns, and embedded this pattern as synchronization...
This paper presents two parallelization methods for H.264 video decoder software on an embedded multicore processor. In parallelizing the H.264 video decoder software on a typical embedded multicore processor with shared memory, there are two problems. One problem is the computational load imbalance among cores. The other problem is memory access contention. The first method is coarse, flexible partitioning...
Manchester code is widely used in industrial control applications as a method of communication. Its encoder and decoder is usually designed based on PLL, which make the circuit complicated. This paper introduces a novel Manchester encoder and decoder based on CPLD. The experimental results proved that, the design is correct, easy to be implemented and easy to be integrated in the existing system.
Many video codecs rely on a periodically embedded codes to maintain synchronization. In order to increase system robustness, we propose a detection algorithm to determine synchronization code location. The associated metric relies on knowledge of the distribution of the locations of codes within the compressed data. These distributions are modeled as functions of sequence type and compression rate,...
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