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Reliability analysis is one of the important foundations in engineering to optimize system performance. A multi-unit system with one dominant unit and numerous secondary units is proposed through practical problems, in which, the secondary units form a m-out-of-n voting system, with load-sharing units and time-varying failure. Furthermore, the type-I failure interaction exists between the dominant...
The Metro system is an important index of a modern city. The quality, performance and safety of Metro systems are highly monitored because of their huge cost, complex engineering and long building time. Signaling (SIG) provides train with the Automatic Train Control (ATC) function in order to satisfy the needs of high transportation, high efficiency, safety and comfort. SIG also supervises train operations...
The exponential distribution is widely used in studies of reliability engineering as a model for life, largely because of its mathematical simplicity. But a mechanical product's life distribution is not in obedience to exponential distribution generally. To find how an exponential distribution can be applied in the high-speed rotating machine's life study, which has the characteristic of wear and...
In this paper, two kinds of new failure criteria of the railway sleeper system are constructed, and the reliability forecast method for the new sleeper system is given. Numerical example shows that the reliability forecast methods that constructed in this paper is efficient for the new sleeper system.
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
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