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This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrection for the widely used class of odd-weight column codes is derived and actual codes which are very close to that theoretical bound are presented...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
This paper presents an FPGA implementation of the vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock...
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