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A novel structure of current controlled negative resistance is presented in this paper. It has a very useful role in many analog circuits like oscillators and bandpass filters. The negative resistance circuit, which requires no external passive component, is constituted of two simplified negative second generation current controlled conveyors (CCCII−). This conveyor uses NPN bipolar transistors to...
This paper describes a 2.4GHz low noise amplifier (LNA) intended for use in receiver system. The design has been done in 180nm technology using CMOS. The proposed LNA uses inductive degeneration technique. This amplifier provides a forward gain of 15.72dB with a low noise figure of .307dB while drawing 6.5mW from 1.8V supply voltage. The LNA uses a transformer as load. This paper presents a detailed...
A Low-Temperature-Drift High-precision band-gap reference current source is developed. A reference voltage is generated by using the positive and negative characteristic of the crystal triode itself. The Power Supply Rejection Ratio is improved by using an operational amplifier which constitutes the degenerate loop. The temperature effect on the band-gap current is reduced by using an off chip resistor...
This paper describes a novel bandgap reference with high PSRR over a wide frequency range. The design utilizes an internally regulated supply voltage without high gain feedback loop. Thus improve PSRR even at high frequency. Additional transistors are added to further improve supply rejection and minimize the second order effect. The circuit is implemented in 0.25 μm CMOS technology. It generates...
In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple mirror/source structure with input and output voltage requirements less than that of a simple current mirror is presented. It can be also used as variable negative impedance converter (variable-NIC) by modifying amplifier transistors' aspect ratios. The circuit's principle of operation is discussed and compared...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
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