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The paper is to implement high-speed serial communication between FPGAs with 8B/10B protocol. High-speed data transmission or data bus often use 8B/10B protocol, such as Serial ATA, PCI Express, Fiber Channel, Internet. In general the development platform of FPGA has built-in 8B/10B IP core, such as the Quartus II and ISE, i.e. the 8B/10B IP core will be limited by different platforms. In this paper,...
A Data Acquisition System (DAQs) is an indispensable part to receive, store and further analysis of data. This paper focuses on Data Acquisition from multiple channels using Dual Data Rate (DDR) techniques. Multiple Channels of data source which are source synchronous are initially configured using Serial Peripheral Interface (SPI) commands. The Proposed technique gives an advantage of storing data...
The DSP + FPGA architecture has been widely used in embedded systems, and the high-speed and real-time communication method between DSP and FPGA is the key point of this architecture. The paper describes the typical high-speed communication interfaces including EMIF(External Memory Interface), uPP(Universal Parallel Port), RapidIO (Serial Rapidio, SRIO) and PCIe (PCI Express), focuses on the schemes...
The Inter — Integrated Circuit bus commonly called as I2C (I squared C) or I2C bus is a serial bus invented by Philips Semiconductors during early 80's for interconnecting integrated circuits. It consists of only two active wires called SDA and SCL. In this paper, the design and implementation of a dual master — dual slave I2C bus controller is presented. The bus controller design is implemented using...
Based on the first prototype, a newly modified trigger multiplexer module (merger) is under development for the Central Drift Chamber (CDC) detector which will be used in the future Belle II experiment. The features of modified merger circuit board include two Arria II FPGAs, four 3.125G optical modules and one 6.25G optical module for data transmission. The modified circuit board of merger was made...
Data storage device system plays a very important role in data analysis and scientific research. This paper designs and implements an data storage device system based on FPGA and DSP. The device of DSP controls the transmit and storage of data in the device of Flash. The device communicates with device through the implementation of hardware and the standard protocol of HDLC is realized on FPGA. The...
In order to promote the development and application of PROFIBUS-DP in domestic industrial control process, in order to improve the reliability, anti-interface and low-power of the control system, an embedded PROFIBUS-DP slave station controller based on NIOS II has been designed in this paper. A chip of FPGA is selected as the hardware on which the controller has been realized. NIOS II CPU embedded...
This paper describes a design of network remote control based on Ethernet controller RTL8019AS and FPGA chip EP3C25Q240C8N. It's through the Altera NIOS II soft-core processor and a simplified TCP/IP protocol LWIP to complete the Ethernet Communication Protocol, and FPGA can configure and control RTL8019AS. Then the information can be communication between FPGA and PC, in order to achieve network...
Point-to-point connectivity through FPGA high-speed serial I/O is an important component for many space-based applications. The susceptibility of high-speed transceivers to soft errors is still under investigation and is a matter of concern in reliable point-to-point communications. This work develops a technique to provide full-bandwidth, lossless data transmission across high-speed transceivers...
Nowadays, long-distance data transmission is one of the key features for remote sensing systems such as seismic exploration. In these kinds of systems, ordinary twisted pair is more suitable than fiber optics because of working environments or limited costs. But there are two limitations as long distance and data transmission speed which are not easy to be improved in these systems. We designed and...
SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers. In conformity with design-reuse methodology, this paper introduces high-quality SPI Master/Slave IPs that incorporate all necessary features required by modern ASIC/SoC applications. Based upon Motorola's SPI-bus specifications, version V03.06, release February 2003, the...
Gigabit Ethernet technology has become the mainstream now, and many applications also require real-time transmission of high-speed data, so how to realize gigabit ethernet interface becomes a new topic. This paper proposes and implements an embedded system based on RTL8169SC and FPGA. PCI interface logic is embedded in FPGA, therefore the single FPGA includes both user logic and interface logic.The...
The communication mechanisms employed in systems on a single chip(SoC) are an important contribution to their overall performance. To date, bus-based paradigm is applied in many areas of real-time applications of SoCs realizing on FPGA due to its flexibility and simplification in designing tool. Although offering the module-increasing flexibility, its bandwidth and scalability still become problem...
Aimed at the non-standard Flash memory composed of 8 K9KAG08U0M Flash chips of Samsung Company, the paper introduces a high-speed data transfer interface with FPGA (Field Programmable Gate Array) as the main controller. With the synchronous DMA (Direct Memory Access) mode of USB2.0, the system implements the management, reading and transmission of the data in the memory. The design of the system proves...
Systematic idea is very basilic in the integrated circuit design, interface between modules is especially important. Serial Peripheral Interface (SPI) is an interface that facilitates the transfer of synchronous serial data, which is engineer's favorite for its convenience and saving system resource. In this paper introduce a new design method, and simulation and realization in FPGA.
This paper presents design and implementation of a data acquisition system (DAS) in field programmable gate arrays (FPGA) using system on chip (SoC) methodology. To ensure the reliability of data being transmitted over the channel, a suitable framing interface along with error detection is proposed and interfaced with Xilinx Aurora IP core. The proposed DAS is capable of transmitting the data @ 1...
Considering that ordinary ZigBee based systems operate at a rate of 250 kbps, which imposes various limitations on their applications, and that there are 16 independent channels at 2.4 GHz, this paper presents a novel approach of FPGA controlled, ZigBee protocol based multi-frequency high speed wireless Ad Hoc network. The system employed five individual ZigBee modules around a FPGA controller, merging...
The development of a new tri-modality preclinical Computed Tomography apparatus (??CT), Single Photon Emission Computed Tomography apparatus (??SPECT) and Positron Emission Tomography apparatus (??PET) dedicated to small animal imaging tomography is underway in the group ImaBIO at the Institut Pluridisciplinaire Hubert Curien. The ??CT and ??SPECT scanners are working quite fine and now used by biologists...
USB-based portable measurement instrument has becoming more and more popular in field application. Recently, isolated RS-485 based synchronous data link control (SDLC) connection was used in aerospace payloads. Custom versions of SDLC protocol was designed for optimizations of specific applications, so do the SDLC protocol measurement units. A USB-based SDLC protocol measurement unit's design is presented...
In this paper, we present the design of a GALS wrapper used in Network on Chip (NoC) based on standard cells. The GALS wrapper includes two communication ports, 4-phase handshake circuits, data buffer and signal synchronizer. The detailed design methodology of GALS wrapper is given and the circuits are validated with Verilog-HDL and implemented in FPGA. The simulation results show that the wrapper...
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