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Ethernet ring protection (ERP) introduced by ITU-T G.8032 Recommendation is a new class of packet switched network protection technology that can provides ring automatic protection switch for nested multiple Ethernet rings. An ERP system is required to provide network protection against link and node failures within 50 ms. Whenever the protection scheme switches the ring to have a new topology, the...
Network-on-chip mapping and the configuration of the communication parameters are critical process of the NoC design. They significantly influence the performance, area and power of the NoCs. We take the NoC mapping problem and the design of the communication parameters both into account. First, we formalize the problem of NoC mapping. Then we propose an analytical delay model based on wormhole switching...
A fast rerouting scheme is proposed to guarantee the QoS performance of rerouted path when handling link and node failures. The new scheme is based on deflection routing mechanism and improves on two aspects: first, it can promptly handle single node failure as well as single link failure, second, QoS metric is taken into accounted when calculating recovery routes. Simulation results show that the...
This paper studies consensus problems of multiple second-order agents with time-varying topology. It is assumed that each possible interaction topology is strongly connected and balanced and each agent can only obtain the measurements of its position relative to its neighbors. A feasible protocol is proposed, and by applying the linear matrix inequality technique and the common Lyapunov function approach,...
In modern system-on-chips the communication architecture is a crucial part of the design for performances and power constraints because the number of modules is increasing due to continuous integration scale. Network-on-Chip (NoC) architecture lets to obtain greater performances over the traditional communication architectures. NoC design is more complex because there are more components and networks...
As the number of processing nodes on chip multi-processors (CMPs) keeps increasing, providing efficient communication with the on-chip interconnect becomes increasingly critical. With 32-core CMP designs on the drawing table of engineers, there is a demand for accurate simulation models that capture all the complexities and interactions of the different design layers including the application, operating...
Most network operators have considered reducing Label Switched Routers (LSR) label spaces (i.e. the number of labels that can be used) as a means of simplifying management of underlaying Virtual Private Networks (VPNs) and, hence, reducing operational expenditure (OPEX). This letter discusses the problem of reducing the label spaces in Multiprotocol Label Switched (MPLS) networks using label merging...
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