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This paper presents a hands-on advanced logic design course using digital music synthesis as the basis of all homework and labs. A Verilog-based design flow is coupled with a FPGA development board, a digital to analog converter, and a small amplifier which enables a complete progression of specification, implementation and verification over the 10 week quarter. The gratification of hands-on audio...
Circuits implementing the concept of Selective Fault Tolerance according to are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic,...
This paper presents the design and implementation of a hardware graphical display custom processor for generating and manipulating plots based on a given set of time varying input signals. The paper primarily focuses on the design to generate plots of two sampled sine waves of 5 KHz and 10 KHz respectively, along with horizontal and vertical axes with proper scaling. This was achieved by designing...
Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace “standard” sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these laboratories. First, students have some difficulties in understanding...
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. The feature allows multiple...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for parameter modifications or do not allow the design to be run at full-speed. Designs are frequently first modeled using a high-level language then later...
With the advent of increasingly complex systems, the use of traditional power estimation approaches is rendered infeasible due to extensive simulation times. Hardware accelerated power emulation techniques, performing power estimation as a by-product of functional emulation, are a promising solution to this problem. However, only little attention has been awarded so far to the problem of devising...
Gigabit Ethernet technology has become the mainstream now, and many applications also require real-time transmission of high-speed data, so how to realize gigabit ethernet interface becomes a new topic. This paper proposes and implements an embedded system based on RTL8169SC and FPGA. PCI interface logic is embedded in FPGA, therefore the single FPGA includes both user logic and interface logic.The...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
Hardware-and-software full system co-verification and co-simulation in the early stage of SoC development, i.e., before HDL code synthesis, is usually a big challenge for design engineers. In this paper, we propose a QEMU-based full system simulation framework to tackle the problem faced with the design of an embedded multi-view 3D GPU (graphic processing unit). Through the framework, we are able...
The latest generation of FPGA devices offers huge resource counts that provide the headroom to implement large-scale and complex systems. However, this poses increasing challenges for the designer, not just because of pure size and complexity, but also to harness effectively the flexibility and programmability of the FPGA. A central issue is the need to integrate modules (IP blocks) from diverse sources...
The coupling architecture containing an FPGA device and a microprocessor has been widely used to accelerate microprocessor execution. Therefore, there have been intensive researches about synthesizing high-level programming languages (HLL) such as C and C++ into HW in the high-level synthesis community in order to make the work of reconfiguring the FPGA easier. However, the difference in a calling...
Today's machine automation systems are demanding for better throughput, faster response, built in safety features and high speed communication support, besides satisfying IEC61131-3 control specification. MEMS sensors & actuators along with increased control logic complexities are stretching limits of conventional Programmable Logic controllers (PLCs) generally used for industrial and high end...
DCT/IDCT finds potent application in the field of image and signal processing. In this paper, we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low...
Turbo code is a class of convolutional codes which have great deal of interest as they attain the ultimate limits of the capacity of communication channel. They are known as ??The ultimate Error Control Codes?? which made them move rapidly from research laboratories to practical applications throughout the world. The use of these codes has been proposed for several applications where highly reliable...
In this paper, I introduce my and my students projects to reincarnate historic systems on FPGA. Our projects are not replica nor paper-model of historic systems, but reorganized and working system on FPGA with novel and progressive design methodology. I mean progressive as under the development, because I have developed them and I am still improving the methodology and tools very often to use them...
Current practices for the design and deployment of hardware redundancy techniques in embedded systems remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging problems of engineering fault tolerance mechanisms in a generic way and providing suitable tools for coping with their deployment. This approach relies on metaprogramming to specify...
The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically...
The ongoing miniaturization of digital circuits makes them more and more susceptible to faults which also complicates the design of fault tolerant systems. In this context fault injection plays an important role in the process of fault tolerance validation. As a result many fault injection tools have emerged during the last decade. However these tools only operate on specific domains and can therefore...
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