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This paper presents a QEMU and SystemC-based virtual platform that is capable of hardware modeling using TLM-2.0 interface. The proposed virtual platform is not only capable of running an operating system, but it is also capable of using such an interface to connect hardware models, such as the instruction set simulator to a bus model. We verify the functionality of such a platform by using it to...
Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware...
A highly modular framework for developing parallel H.264/AVC video encoders in multi-core systems is presented. Such framework implements an efficient hardware/software co-design methodology, which enables replacing the software implementation of any operation in the video encoder application by a corresponding system call to a hardware accelerator. To achieve such goal, this design strategy adopts...
The set of all possible design alternatives for a system is referred to as a design-space, and design-space exploration (DSE) is the systematic exploration of the elements in a design-space. Various DSE techniques have been used for hardware/software co-design, configuration of software product lines and real-time software synthesis. Although at an abstract level DSE steps performed in these domains...
A System-on-Chip Design of VLD (Variable Length Decoder) in multi-standard video decoder is proposed in this paper. Our design supports all the popular video compression standards, e.g. MPEG-1, MPEG-2, MPEG-4, H.264, AVS, RealVideo. Benefit from its low power, the design is especially suitable for wearable multimedia applications. Simulation results show that the whole design takes an area of 1.04mm2,...
In this paper we propose a synthesis semantics for SystemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for SystemC primitive channels that allows deterministic access scheduling and user-constrained refinement...
Word-level bounded model checking and equivalence checking problems are naturally encoded in the theory of bit-vectors and arrays. The standard practice of deciding formulas of such theories in the hardware industry is either SAT- (using bit-blasting) or SMT-based methods. These methods perform reasoning on a low level but perform it very efficiently. To find alternative potentially promising model...
Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesign. Due to shortening time-to-market demands, ??first time right?? requirements have thereby to be satisfied. In this paper, we propose an approach that makes use of Boolean satisfiability for verifying UML/OCL models. We describe...
The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years...
The discrete wavelet transform (DWT) and the embedded block coding with optimized truncation (EBCOT) account for most of the workload in JPEG2000 encoding. This paper presents a new hardware & software co-design that improves the JPEG2000 encoder's performance while keeping its flexibility by replacing the DWT and the EBCOT with hardware accelerators. In order to further improve the performance,...
Due to the local smoothness characteristic of most real-world object surfaces, the per-pixel depth information can be efficiently compressed instead of using an additional color video channel. However, the complexity and hardware requirement are nearly two times higher than coding 2D video. By using sharing-of-motion-information method and analyzing the relationships between texture video and depth...
This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of...
Hardware/software partitioning plays significant role in the field of SoC design. One of the primary steps of the Hardware/software partitioning is to represent search space solutions. Under the existing work, the search space solutions are represented with binary coding or integer coding. However, with the increasing of SoC scale, the partitioning performance of these coding will have greatly affection...
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