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All-digital phase-locked loops (ADPLLs) are inherently multi-rate systems with time-varying behavior. In support to this statement accurate multi-clock domain models of ADPLL frequency synthesizers are presented. Their analytically derived phase transfer characteristics accurately predict second order effects (such as spectral aliasing) that are not captured using conventional modeling approaches...
We propose an all-digital offset PLL architecture in which the RF oscillator output is frequency translated through rotation of its quadrature phases before being fed back for the phase comparison with the frequency reference. This eliminates spurious tones caused by the finite resolution of the phase detection process when the synthesized frequency is very close to the integer-N multiple of the reference...
A new phase-domain all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. In this brief, we propose time-domain modeling and simulation techniques of the ADPLL that are well suited for system analysis using high-level programming languages, e.g., Matlab. They are based on the event-driven principles inherent in hardware description...
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