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Timing analysis in embedded systems has focused mainly on the Worst-Case Execution Time (WCET) in the past. This was (and still is) important to make guarantees for the application of the system in safety critical environments. Today, two reasons call for a slightly changed perspective. Firstly, the complex and often unpredictable internal structure of modern system-on-chip architectures prohibits...
Overheads due to context switching and external interrupt management are core characteristics for Real-Time Operating Systems (RTOS) since they play a central role in their performance and timeliness. In this paper we evaluate two core characteristics for the Real-Time Executive for Multiprocessor Systems (RTEMS), an operating system used for supporting space applications. Our assessment makes use...
This paper presents a scalable design and verification methodology for FPGA-based motor drives for aircraft application, working at high-temperature environment. ProASICPlus from Actel Family (0.22 μm digital CMOS 4 Layer Metal Flash-Based CMOS Process) was chosen to implement the studied motor drive which consists on a current control. The design is implemented at a frequency of 24 MHz and junction...
In video encoding hardware system based on camera link interface, in order to coordinate data transmission between different clock domains, we designed a DSP and FPGA interconnection scheme, in which a software FIFO was used. This article introduced relevant interface interconnects and timing analysis. The system we are using proved the method introduced in the article is stable and efficient to guarantee...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
We present a Built-In Self-Test (BIST) approach for testing and diagnosing the embedded digital signal processors (DSPs) in Xilinx Virtex-4 series Field Programmable Gate Arrays (FPGAs). The BIST architecture and configurations needed to test these programmable DSPs in all of their modes of operation are presented along with fault injection and timing analysis of the BIST configurations.
Stream architecture research is often hindered by slow software simulations. Simulators based on FPGA are much faster. However, larger scale stream architecture simulation needs more FPGA resource, which may result in more FPGA chips or larger capacity FPGA chip would be used. It not only increases the complexity of design, but also increases the cost of research. This paper proposed FPGA-based equivalent...
One of the key-points in system on chip (SoC) design is to have the proper clock oscillator. Currently the most used are RC and quartz oscillators. They feature different characteristics in terms of performance, power consumption and cost, both oscillators have their own advantages and drawbacks. Sometimes SoC design would benefit to have both solutions in order to best cope with all requirements...
Embedded elements, such as block multipliers, are increasingly used in advanced field programmable gate array (FPGA) devices to improve efficiency in speed, area and power consumption. A methodology is described for assessing the impact of such embedded elements on efficiency. The methodology involves creating dummy elements, called virtual embedded blocks (VEBs), in the FPGA to model the size, position...
The paper describes the implementation of a novel approach to ultrasonic ranging systems based on a modified frequency variations monitoring technique. The whole system is developed on a single-chip FPGA, which serves both roles as generator of the specialized signal and as timing analysis hardware in the receiver module. Details of the different tasks and operations which form the structure of the...
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